Question : Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ? Answers: The 5 stages... Read More

MESI is a protocol actually.. cache coherency or a memory coherency. It supports write-back cache. Read More

If the signal coming to the to the synchronous state machine is generated in different clock domain than the state machine clock. This avoids the metastability of the coming signal. Read More

A type of cache with the following feature: when changes are made to cached data, they are not simultaneously made to the original data as well. Instead, the changed data is marked, and the original data is updated when the chached data is... Read More

There are three types of buses. 1. Address bus: This is used to carry the Address to the memory to fetch either Instruction or Data. 2 .Data bus : This is used to carry the Data from the memory. 3. Control bus : This is used to carry the... Read More

Byte contains 8 combinations of bits. Read More

To improve the performance of proceesor computer system. In many cases some memory locations are access frequently and updated and it take around 30ns to access from main memory (SRAM). Instead if it is cached (DRAM ~ 10ns) then access is faster. Read More

There is a fine difference between these two operators. Actually = opearator is used to assign a value to a variable or it is used to transfer the value from one variable to another variable. And == operator is used in IF loop. Read More