The comparison can be made out of two factors 1) Performance and 2) Integrity of Data Write through is better in integrity as it will flush for each writes. Write back holds up the write till the same cache line has to be used up for a read,... Read More

64k/32 = 2000 blocks 2 way set assoc- 2000/2 = 1000 lines-> 10 bits for index 32B block-> 5 bits for block offset 32-10-5= 17 bits for tag Read More

Cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence. When clients in a system, particularly CPUs in a multiprocessing system cache occurs Read More

With "n" stage pipeline the throughput should be "n" instructions. As the pipe stages can't be perfectly balanced ( time to perform task in a pipeline stage), furthermore pipeline does involve some overheads. Read More

The MESI protocol is also known as Illinois protocol due to its development at the University of Illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol. MESI is the most common protocol which supports... Read More

It turns out that caching is an important computer-science process that appears on every computer in a variety of forms. There are memory caches, hardware and software disk caches, page caches and more. Virtual memory is even a form of caching.... Read More

Like java have a feature for handling exception handling "prime catch".the exception like divide by zero,out of bound. Read More

There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. There are three classes... Read More

A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed. That is, several instructions are in the pipeline simultaneously, each at a different processing stage. Read More

The instruction sets can be differentiated by * Operand storage in the CPU * Number of explicit operands per instruction * Operand location * Operations * Type and size of operands Read More

65 to decimal 65/16=4 remainder=1 ==41 decimal decimal to binary 101001 Read More

1)address lines to refer to the address of a block 2)data lines for data transfer 3)IC chips 4 processing data Read More

65 to decimal 65/16=4 remainder=1 ==41 decimal decimal to binary 101001 Read More

A technique used in advanced microprocessors where the microprocessor begins executing a second instuction before the first has been completed. That is, several instructions are in the pipeline simultaneously, each at a different processing stage. ... Read More

DNS cache snooping is not a term the author just made up, it is known and discussed by some notable DNS implementation developers, and a few interested DNS administrators have probably at least heard of it. Read More

Virtual memory is a concept that, when implemented by a computer and its operating system, allows programmers to use a very large range of memory or storage addresses for stored data. The computing system maps the programmer's virtual... Read More

Arise a non maskable interrupt. Then give jump instruction to required subroutine. Read More

Subroutine are the part of executing processes(like any process can call a subroutine for achieve task),while the interrupt subroutine never be the part.interrupt subroutine are subroutine that are external to a process. Read More

First convert a number into binary format. Then keep last binary number as it is & complement all others. Eg:- 1101001 2's Compl:0010111 Read More

Subroutine are the part of executing processes(like any process can call a subroutine for achieve task),while the interrupt subroutine never be the part.interrupt subroutine are subroutine that are external to a process. Read More

With "n" stage pipeline the throughput should be "n" instructions. As the pipe stages can't be perfectly balanced ( time to perform task in a pipeline stage), furthermore pipeline does involve some overheads. Read More